1. Field
The present invention relates to a semiconductor device.
2. Description of Related Art
Unlike a hard error that destroys a specific part of a circuit permanently, a soft error refers to a transitory, recoverable malfunction that randomly occurs in a semiconductor chip. The malfunction is attributable to incidence of neutron beams of secondary cosmic rays or alpha rays or the like from an LSI material upon an LSI.
Various measures for soft errors are currently being invented. One of most effective and common measures is a method of adopting a circuit configuration that prevents the occurrence of an error from influencing the system. For example, an ECC (Error Correction Code) can correct errors relatively easily. However, these measures or methods cause an increase in the area and are not applicable to a logic circuit. Therefore, if the soft error rate increases along with the degree of integration, there is a high probability that problems of soft errors may become more serious than ever.
A general soft error prevention means is described in Japanese Patent Laid-Open No. 2005-191454. This method adds a capacitance to a data holding node and thereby prevents data inversion caused by the occurrence of charge based on radiation. Applying this method to a latch circuit will cause performance deterioration in a setup time and delay time or the like.
Furthermore, Japanese Patent Laid-Open No. 10-335992 describes a semiconductor integrated circuit device provided with flip flops including first and second logic gates that make up a first latch by being substantially cross coupled, a third logic gate that makes up a second latch by being substantially cross coupled with the first logic gate or a fourth logic gate that makes up a third latch by being substantially cross coupled with the second logic gate.
Furthermore, Japanese Patent Laid-Open No. 2006-129477 describes a tri-state capable latch to reduce soft errors provided with a) a first inverter having an input and output and b) a second inverter having an input and output, wherein c) the input of the first inverter is connected to the output of the second inverter, d) the input of the second inverter is connected to the output of the first inverter, and e) when the input to the second inverter is blocked by a soft error event, the second inverter is set to a tri-state by a certain signal.
Furthermore, Japanese Patent Laid-Open No. 04-372214 describes a latch circuit including a first OR circuit, a first input terminal which receives a data signal and a second input terminal which receives a clock signal, a gate circuit that receives the clock signal and outputs the same logic as the clock signal, a second OR circuit, a first input terminal which receives the output of the first OR circuit and a second input terminal which receives the output of the gate circuit, a third OR circuit, a first input terminal which receives an inverted clock signal corresponding to the inverted clock signal and an AND circuit, a first input terminal which receives the output of the second OR circuit, a second input terminal which receives the output of the third OR circuit and the output which is supplied to a data output terminal and the second input terminal of the third OR circuit.